1. Field of the Invention
The present invention relates to a semiconductor memory, and more particular to a nano tube cell using a PNPN diode as a unit switch device, and a semiconductor device having a double bit line sensing structure which can induce a sensing voltage of a main bit line by using a current gain according to a cell data.
2. Description of the Background Art
In a gigabyte-level DRAM, a memory capacity increases, a cell size decreases, and a cell capacitance decreases.
In order to stably operate a memory having a small cell capacitance, a capacitance of a bit line must be reduced. It is not easy to reduce the capacitance of the bit line in a high integration memory. In addition, an interval between the bit lines is small in the high integration memory. As a result, unnecessary power consumption may be caused by short channels in a cell structure using an NMOS transistor.